1. Field of the Invention
The present invention relates to a low-noise, high-gain semiconductor integrated circuit device comprising bipolar transistors, and method of designing such a low-noise high-gain semiconductor integrated circuit device.
2. Description of the Related Art
In recent years, high-frequency amplifiers which are characterized by a low power requirement, low noise, and a high power gain have become more important for use in the field of mobile communications. Bipolar transistors used in such high-frequency amplifiers are required to have better noise and gain characteristics. It is important for such high-frequency amplifiers to reduce an overall noise figure. Therefore, high-frequency amplifiers need to have improved noise characteristics while maintaining a desired power gain for transistors that are used. However, since there is a trade-off between the power gain characteristics and noise characteristics of transistors, it is difficult to manufacture transistors which satisfy desired power gain characteristics and noise characteristics at a low cost.
Japanese laid-open patent publication No. 7-254608 discloses bipolar transistors having the same emitter area. The disclosed bipolar transistors include a transistor structure having good noise characteristics in a certain current range and a transistor structure having a good gain. These transistor structures are used in different circuits.
FIGS. 1(a) through 1(f) of the accompanying drawings show bipolar transistors disclosed in Japanese laid-open patent publication No. 7-25408. FIGS. 1(a) through 1(c) are plan and cross-sectional views and an equivalent circuit diagram, respectively, of a bipolar transistor having a single emitter structure, and FIGS. 1(d) through 1(f) are plan and cross-sectional views and an equivalent circuit diagram, respectively, of a bipolar transistor having a multiple emitter structure. As shown in FIGS. 1(b) and 1(e), an n.sup.+ embedded layer 111 and an n collector layer 112 are successively disposed on a p Si substrate 110, and a base layer 113, an emitter layer 114, and a device separating insulative film 115 are successively disposed on the n collector layer 112.
In FIGS. 1(a) through 1(c), a single emitter layer 114 is disposed in the base layer 113. In FIGS. 1(d) through 1(f), two emitter layers 114 are disposed in the base layer 113. Each of the emitter layers 114 of the multiple emitter structure has a width half the width of the emitter layer 114 of the single emitter structure. However, the total emitter area of the single emitter structure is the same as the total emitter area of the multiple emitter structure.
FIG. 2 of the accompanying drawings shows the relationship between the collector current, and the noise figures and power gain of the conventional bipolar transistors shown in FIGS. 1(a) through 1(f). As shown in FIG. 2, the multiple emitter bipolar transistor having the plural emitters has a lower noise figure than the single emitter bipolar transistor having the single emitter in a certain collector current range. On other hand, the power gain of the single emitter bipolar transistor is better than the multiple emitter bipolar transistor in all collector current ranges. Instead of improving these noise figure and power gain characteristics through device and circuit approaches, these two bipolar transistors are simply used in different circuits.
The conventional bipolar transistors suffer the following disadvantages:
First, it is not easy to distinguish a device section where more importance should be attached to the power gain characteristics from a device section where more importance should be attached to the noise characteristics in a circuit, and hence device designing is complicated.
Secondly, the total emitter area in the single emitter bipolar transistor is the same as the total emitter area in the multiple emitter bipolar transistor. That is, these bipolar transistor have different emitter lengths, indicating that there are a plurality of bipolar transistors having different emitter structures in a circuit.
The conventional bipolar transistors are not of a so-called self-aligned structure with a base region constructed of polycrystalline silicon or the like. Generally, it is important for bipolar transistors which operate in a high-frequency range such as a GHz range to have improved high-frequency characteristics by reducing the base resistance. Therefore, bipolar transistors with a base electrode constructed of polycrystalline silicon are more preferable in terms of a noise figure and a power gain than the conventional non-self-aligned bipolar transistors. Bipolar transistors having a shorter emitter width tend to suffer a plug effect on emitters because the aspect ratio of an emitter contact is greater than the non-self-aligned bipolar transistors.
The plug effect is a phenomenon in which when an impurity is diffused from an emitter region, the impurity is subject to less diffusion in a transistor structure with a smaller emitter width than in a transistor structure with a greater emitter width. Usually, the thermal history of a transistor is adjusted in the fabrication process to optimize the depth of an emitter-to-base junction of a transistor structure with a smaller emitter width in view of the plug effect. Therefore, in a transistor structure with a greater emitter width, an emitter impurity is diffused more deeply due to the plug effect, tending to cause a punchthrough between the emitter and the collector. For this reason, it is important to employ a single fixed transistor size in a circuit for the stable fabrication of transistors with a high yield.